The present invention relates generally to non-volatile memory cell arrays and in particular to counteracting coupling effects during the operation of such arrays.
In a typical array of non-volatile memory cells, such as those disclosed in U.S. Pat. No. 5,289,411, signal carrying regions or conductors include word lines (WL), bit lines (BL), and source lines (SL), which run parallel and/or transverse to one another. Storage circuits are sometimes provided to communicate with ones of these lines to provide signals or voltage levels required during an operation of the device. For example, latches can be provided to communicate with the source lines to supply a high voltage level during a programming operation. The physical arrangement of the various signal-carrying regions of the device can result in coupling, capacitive or otherwise, of signals or noise from one region to another, even though such coupling is unintended. As is well known in the art, capacitive coupling between conductive regions is inversely proportional to the separation between the conductive regions, and directly proportional to the area of portion of the conductor regions opposite each other. Thus, as devices are scaled down and circuitry becomes more tightly packed, coupling effects will increase.
It has been found that such coupling can interfere with the proper operation of the device, for example, by causing voltages or signals to be induced or coupled onto unintended conductive regions or components of the device, which in turn can result in improper operation of the device and possibly outright device failure. As an example, the above mentioned latches can be accidentally set by the coupled or induced voltages or signals, thereby causing the device to malfunction. There is therefore a need to provide a non-volatile memory cell array and method for operating such array in which such unintended coupling and accidental setting of latches is counteracted.
The above and other problems and disadvantages of prior non-volatile memory array devices and methods of operation are overcome by the present invention of a method and apparatus for programming a non-volatile memory array of the type which includes a plurality of bit lines, a plurality of word lines, and a plurality of source lines, and a plurality of temporary storage circuits which can be set to supply a desired state for use in connection with operations involving designated non-volatile memory cells, wherein each of the plurality of temporary storage circuits communicates with a different one of a plurality of groupings of the non-volatile memory cells by way of associated word and source lines. In one embodiment of the present invention, the method comprises the steps of precharging unselected bit lines to a program inhibit level, as a part of a programming operation, inhibiting the operation of the plurality of temporary storage circuits during a first portion of the precharging step, and setting ones of the plurality of temporary storage circuits to desired states following the first portion of the precharging step. In a further embodiment of the method the temporary storage circuits are set to a program state in response to an enable signal, and the inhibiting step includes the steps of setting the source lines at a reference potential during an initial portion of the precharging step, and withholding the enable signal from the temporary storage circuits during the initial portion of the precharging step. The withholding step can include the step of applying a disable signal to the temporary storage circuits during the initial portion of the precharging step.
In another embodiment of the present invention the method comprises the steps of precharging unselected bit lines to a program inhibit level, at a rate which is selected to reduce coupling effects between the unselected bits lines and word lines or source lines, as a part of a programming operation, and programming selected non-volatile memory cells according to states set in the plurality of temporary storage circuits. The step of precharging the bit lines to a program inhibit level can include the step of adjusting the rate of the precharging so that the bit lines reach the program inhibit level in approximately a program initialize period.
In a further embodiment of the present invention, the method for programming comprises the steps of arranging each of the plurality of temporary storage circuits to be responsive to a minimum number of word lines associated with the selected sector during a period in which unselected bit lines are precharged, precharging unselected bit lines to a program inhibit level, as a part of a programming operation, and programming selected non-volatile memory cells. The method can include the step of arranging each of the plurality of temporary storage circuits to be responsive to only one word line of the associated selected sector during the period in which the unselected bit lines are precharged.
The apparatus of the present invention implements the methods of the present invention.
These and other features and advantages of the present invention will be more readily understood upon consideration of the following detailed disclosure of the invention and accompanying drawings.